Recently, semiconductor devices such as flash memories, DRAMs, and SRAMs have become widely used in many electronic devices. A semiconductor memory device includes a memory cell array having memory cells in a matrix fashion, with data being stored in the memory cells. An external circuit designates an address at which storage data stored in the memory cell array is to be input or output, and then inputs or outputs the data to or from the memory cell array. The input/output of the storage data to/from the external circuit and an input of address data indicating the address are performed via an input/output circuit. The input/output between the external circuit and the input/output circuit is performed in a parallel manner with respect to bits. The number of bits is called the data width, which is 16 bits or 32 bits, for example. The address in the memory cell array at which the storage data is input or output is defined by 25-bit address data, for example. The input/output of the storage data and address data between the external circuit and the input/output circuit is performed via data terminals and address terminals. However, to minimize the number of required terminals, some data terminals also serve as address terminals.
A semiconductor memory device having data terminals also serving as address terminals is now described, with a flash memory being taken as an example of a semiconductor memory device. FIG. 1 is a schematic view of a flash memory that inputs or outputs storage data having a data width of 16 bits, and involves 25-bit address data. A memory cell array 68 and an input/output circuit 69 are provided on a semiconductor chip 60. The input/output circuit 69 is coupled to pads 62 and 63. The pads 62 and 63 are coupled to external terminals 66 and 67 on the package with wires. The pads 62 are pads D0/A0 through D15/A15 that are coupled to external terminals ExD0/A0 through ExD15/A15, which are the external terminals 66. The pads 63 are pads A16 through A24 that are coupled to external terminals ExA16 through ExA24, which are the external terminals 67.
FIG. 2 shows a data structure of data to be input or output between an external circuit and the external terminals 66 and 67. The external circuit includes a system bus also serving as the bus for transmitting address data and storage data. The external terminal ExD0/A0 inputs or outputs the first bit DB0 of the storage data at the time of data input/output. The external terminal ExD0/A0 also inputs the first bit AB0 of the address data at the time of address input. Each of the external terminals ExD0/A0 through ExD15/A15 performs the same as above. In this manner, the external terminals ExD0/A0 through ExD15/A15 serve as data terminals and address terminals. Meanwhile, the external terminals ExA16 through ExA24 are address terminals that only input address data. The pads 62 provided on the semiconductor chip 60 serve as data pads and address pads. Meanwhile, the pads 63 are address pads that input only addresses.
Japanese Unexamined Patent Publication No. 9-231131 discloses a structure in which semiconductor memory devices having address terminals that do not serve as data terminals. The address terminals of each of the semiconductor memory devices are coupled together and the data terminals are coupled to external buses independently of one another. Accordingly, even if the data width of each of the semiconductor memory devices is small, it is possible to cope with external buses with large widths. As such, there is a demand for an increase in data width for inputting and outputting storage data in semiconductor memory devices. However, the production of a semiconductor memory device having a 32-bit data width will require the design and development of new input/output circuits. In such a case, the development period may be long and costly. To counter this problem, two semiconductor chips each having a data width of 16 bits are used to form a semiconductor memory device having a 32-bit data width, as in a first conventional example. With such a semiconductor memory device having a 32-bit data width, the development period can be shortened, and the development cost can be lowered. However, when a semiconductor memory device having a 32-bit data width is formed in a conventional manner using two semiconductor chips that have address terminals serving as data terminals and have a 16-bit data width, the loads on the external terminals become uneven.